Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

09/12/2023
by   Khushal Sethi, et al.
0

In this paper, we present first-ever optimized hardware implementation of a state-of-the-art neuromorphic approach Histogram of Averaged Time Surfaces (HATS) algorithm to event-based object classification in FPGA for asynchronous time-based image sensors (ATIS). Our Implementation achieves latency of 3.3 ms for the N-CARS dataset samples and is capable of processing 2.94 Mevts/s. Speed-up is achieved by using parallelism in the design and multiple Processing Elements can be added. As development platform, Zynq-7000 SoC from Xilinx is used. The tradeoff between Average Absolute Error and Resource Utilization for fixed precision implementation is analyzed and presented. The proposed FPGA implementation is ∼ 32 x power efficient compared to software implementation.

READ FULL TEXT

Please sign up or login with your details

Forgot password? Click here to reset