Toward Terabits-per-second Communications: A High-Throughput Hardware Implementation of G_N-Coset Codes
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Recently, a parallel decoding algorithm of G_N-coset codes was proposed.The algorithm exploits two equivalent decoding graphs.For each graph, the inner code part, which consists of independent component codes, is decoded in parallel. The extrinsic information of the code bits is obtained and iteratively exchanged between the graphs until convergence. This algorithm enjoys a higher decoding parallelism than the previous successive cancellation algorithms, due to the avoidance of serial outer code processing. In this work, we present a hardware implementation of the parallel decoding algorithm, it can support maximum N=16384. We complete the decoder's physical layout in TSMC 16nm process and the size is 999.936μ m× 999.936μ m, ≈ 1.00mm^2. The decoder's area efficiency and power consumption are evaluated for the cases of N=16384,K=13225 and N=16384, K=14161. Scaled to 7nm process, the decoder's throughput is higher than 477Gbps/mm^2 and 533Gbps/mm^2 with five iterations.
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