Abdullah Giray Yağlıkçı | DeepAI

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∙ 09/21/2022

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

DRAM is the building block of modern main memory systems. DRAM cells mus...

0 Abdullah Giray Yağlıkçı, et al. ∙

∙ 10/19/2021

A Deeper Look into RowHammer`s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

RowHammer is a circuit-level DRAM vulnerability where repeatedly accessi...

0 Lois Orosa, et al. ∙

∙ 06/13/2021

Security Analysis of the Silver Bullet Technique for RowHammer Prevention

The purpose of this document is to study the security properties of the ...

0 Abdullah Giray Yağlıkçı, et al. ∙

∙ 02/11/2021

BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

Aggressive memory density scaling causes modern DRAM devices to suffer f...

0 Abdullah Giray Yağlıkçı, et al. ∙

∙ 05/26/2020

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

DRAM is the prevalent main memory technology, but its long access latenc...

0 Haocong Luo, et al. ∙

∙ 10/12/2019

EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM

The effectiveness of deep neural networks (DNN) in vision, speech, and l...

0 Skanda Koppula, et al. ∙

∙ 07/13/2018

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

Main memory (DRAM) consumes as much as half of the total system power in...

0 Saugata Ghose, et al. ∙

∙ 05/08/2018

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

This paper summarizes our work on experimental characterization and anal...

0 Kevin K. Chang, et al. ∙

∙ 05/29/2017

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

The energy consumption of DRAM is a critical concern in modern computing...

0 Kevin K. Chang, et al. ∙

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