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12/24/2018
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Recent attacks have broken process isolation by exploiting microarchitec...
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05/21/2018
Constructing a Weak Memory Model
Weak memory models are a consequence of the desire on part of architects...
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01/19/2018
HGum: Messaging Framework for Hardware Accelerators
Software messaging frameworks help avoid errors and reduce engineering e...
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10/21/2017
BigSparse: High-performance external graph analytics
We present BigSparse, a fully external graph analytics system that picks...
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10/11/2017
Weak Memory Models with Matching Axiomatic and Operational Definitions
Memory consistency models are notorious for being difficult to define pr...
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07/19/2017
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
The memory model for RISC-V, a newly developed open source ISA, has not ...
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05/16/2017
An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution
There has been great progress recently in formally specifying the memory...
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10/06/2016
Validating Simplified Processor Models in Architectural Studies
Cycle-accurate software simulation of multicores with complex microarchi...
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06/17/2016